1. Technical Field
Generally, the present disclosure relates to integrated circuits, and, more particularly, to reductions in noise arising from capacitance of integrated circuit clock trees.
2. Description of the Related Art
Integrated circuits require clock signals to ensure synchronous and effectual operation of their various components. Typically, a phase-locked loop (PLL) provides a synchronized version of a clock signal, and a clock mesh or clock tree distributes various versions of the clock signal to the various components of the integrated circuit. In light of the high power and high frequencies of typical modern clock trees may have to deal with noise issues. For example, clock trees generate significant capacitance, which may give rise to noise that may interfere with proper operation of one or more components of the integrated circuit. Such noise may especially be pronounced during clock gating (e.g., clock enabling, clock disabling) and reset sequencing (e.g., warm resets, scan tests).
Specifically, current consumed in a clock grid can be determined from the equation I=CVF, where C is the clock capacitance, F is the frequency, and V is the voltage. If the frequency of a clock is changed very quickly, such as by rapidly going from a clock-off state to the multiple GHz clock frequencies known for many modern CPUs, the dI/dT will be very high, thus potentially generating noise as discussed above. One source of voltage noise in modern silicon is the die-to-package inductance. Voltage over an inductance L is equal by definition to V=LdI/dT. Voltage noise impacts the speed at which a processor may run.
Known techniques for managing noise in clock trees are undesirably slow for use in modern integrated circuit devices, e.g., computer systems.